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| DG884 Vishay Siliconix 8 x 4 Wideband Video Crosspoint Array DESCRIPTION The DG884 contains a matrix of 32 T-switches configured in an 8 x 4 crosspoint array. Any of the IN/OUT pins may be used as an input or output. Any of the IN pins may be switched to any or simultaneously to all OUT pins. The DG884 is built on a proprietary D/CMOS process that combines low capacitance switching DMOS FETs with low power CMOS control logic and drivers. The ground lines between adjacent signal input pins help to reduce crosstalk. The low on-resistance and low on-capacitance of the DG884 make it ideal for video and wideband signal routing. Control data is loaded individually into four Next Event latches. When all Next Event latches have been programmed, data is transferred into the Current Event latches via a SALVO command. Current Event latch data readback is available to poll array status. Output disable capabilities make it possible to parallel multiple DG884s to form larger switch arrays. DIS outputs provide control signals used to place external buffers in a power saving mode. For additional information see applications note AN504 (FaxBack document number 70610). FEATURES Routes Any Input to Any Output Wide Bandwidth: 300 MHz Low Crosstalk: - 85 dB at 5 MHz Double Buffered TTL-Compatible Latches with Readback * Low rDS(on): 45 * Optional Negative Supply * * * * Pb-free Available RoHS* COMPLIANT BENEFITS * * * * * * * Reduced Board Space Improved System Bandwidth Improved Channel Off-Isolation Simplified Logic Interfacing Allows Bipolar Signal Swings Reduced Insertion Loss High Reliability APPLICATIONS * * * * * Wideband Signal Routing and Multiplexing High-End Video Systems NTSC, PAL, SECAM Switchers Digital Video Routing ATE Systems FUNCTIONAL BLOCK DIAGRAM IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 OUT1 OUT2 8 4 Switch Matrix OUT3 OUT4 Decode Logic, Switch Drivers 4 Disable Outputs WR CS B1 B0 I/O Control Logic Current Event Latches RS SALVO Next Event Latches I/O A3 A2 A1 A0 * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 70071 S-71241-Rev. H, 25-Jun-07 www.vishay.com 1 DG884 Vishay Siliconix PIN CONFIGURATION AND ORDERING INFORMATION OUT1 OUT2 OUT3 6 5 4 3 2 1 44 43 42 41 40 IN2 GND IN3 GND IN4 GND IN5 GND IN6 GND IN7 OUT4 GND GND GND GND GND GND IN 1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 DGND VL RS SALVO WR A3 A2 A1 A0 CS I/O ORDERING INFORMATION Temp Range - 40 to 85 C Package 44-Pin PLCC Part Number DG884DN DG884DN-E3 PLCC and CLCC Top View 18 19 20 21 22 23 24 25 26 27 28 GND GND IN8 DIS 1 DIS 2 DIS 3 DIS 4 V+ B0 V B1 TRUTH TABLE I RS 1 1 1 1 1 1 1 1 1 1 0 I/O 0 0 0 0 0 0 0 0 1 1 X CS 1 0 0 0 X 0 X 0 1 0 X 1 X 1 0 1 1 1 0 1 1 1 0 0 WR SALVO 1 1 1 1 No change to Next Event latches Next Event latches loaded as defined in table below Next Event latches are transparent Next Event data latched-in Data in all Next Event latches is simultaneously loaded into the Current Event latches, i.e., all new crosspoint addresses change simultaneously when SALVO goes low Current Event latches are transparent Current Event data latched-in Both next and Current Event latches are transparent A0, A1, A2, A3 - High impedance A0, A1, A2, A3 become outputs and reflect the contents of the Current Event latches B0, B1 determine which Current Event latches are being read All crosspoints opened (but data in Next Event latches is preserved) Actions All other states are not recommended. www.vishay.com 2 Document Number: 70071 S-71241-Rev. H, 25-Jun-07 DG884 Vishay Siliconix TRUTH TABLE II WR B1 B0 A3 A2 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X A1 0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X A0 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X Next Event Latches IN1 to OUT1 Loaded IN2 to OUT1 Loaded IN3 to OUT1 Loaded IN4 to OUT1 Loaded IN5 to OUT1 Loaded IN6 to OUT1 Loaded IN7 to OUT1 Loaded IN8 to OUT1 Loaded Turn Off OUT1 Loaded IN1 to OUT2 Loaded IN2 to OUT2 Loaded IN3 to OUT2 Loaded IN4 to OUT2 Loaded IN5 to OUT2 Loaded IN6 to OUT2 Loaded IN7 to OUT2 Loaded IN8 to OUT2 Loaded Turn Off OUT2 Loaded IN1 to OUT3 Loaded IN2 to OUT3 Loaded IN3 to OUT3 Loaded IN4 to OUT3 Loaded IN5 to OUT3 Loaded IN6 to OUT3 Loaded IN7 to OUT3 Loaded IN8 to OUT3 Loaded Turn Off OUT3 Loaded IN1 to OUT4 Loaded IN2 to OUT4 Loaded IN3 to OUT4 Loaded IN4 to OUT4 Loaded IN5 to OUT4 Loaded IN6 to OUT4 Loaded IN7 to OUT4 Loaded IN8 to OUT4 Loaded Turn Off OUT4 Loaded 0 0 1 0 0 1 1 0 0 1 0 1 0 1 1 1 0 Notes: When WR = 0 Next Event latches are transparent. Each crosspoint is addressed individually, e.g., to connect IN1 to OUT1 thru OUT4 requires A0, A1, A2 = 0 to be latched with each combination of B0, B1. When RS = 0, all four DIS outputs pull low simultaneously. ABSOLUTE MAXIMUM RATINGS Parameter V+ to GND V+ to VV- to GND VL to GND Digital Inputs VS, VD Current (any terminal) Continuous Current (S or D) Pulsed 1 ms 10 % Duty (A Suffix) Storage Temperature (D Suffix) (A Suffix) Operating Temperature (D Suffix) 44-Pin Quad J Lead PLCCb a Power Dissipation (Package) 44-Pin Quad J Lead Hermetic CLCCc Notes: a. All leads soldered or welded to PC Board. b. Derate 6 mW/C above 75 C c. Derate 16 mW/C above 75 C. Document Number: 70071 S-71241-Rev. H, 25-Jun-07 Limit - 0.3 to 21 - 0.3 to 21 - 10 to 0.3 0 to (V+) + 0.3 (V-) - 0.3 to (VL) + 0.3 or 20 mA, whichever occurs first (V-) - 0.3 to (V-) + 14 or 20 mA, whichever occurs first 20 40 - 65 to 150 - 65 to 125 - 55 to 125 - 40 to 85 450 1200 Unit V mA C mW www.vishay.com 3 DG884 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Specified V+ = 15 V, V- = - 3 V VL = 5 V, RS = 2.0 V SALVO, CS, WR, I/O = 0.8 V V- = - 5 V IS = - 10 mA, VD = 0 V VAIH = 2.0 V, VAIL = 0.8 V Sequence Each Switch On VS = 8 V, VD = 0 V, RS = 0.8 V VD = 0 V, VS = 8 V, RS = 0.8 V VS = VD = 8 V A Suffix - 55 to 125 C D Suffix - 40 to 85 C Unit Parameter Analog Switch Analog Signal Rangee Drain-Source On-Resistance Resistance Match Between Channels Source Off Leakage Current Drain Off Leakage Current Total Switch On Leakage Current Digital Input/Output Input Voltage High Input Voltage Low Address Input Current Address Output Current DIS Pin Sink Current Dynamic Characteristics On State Input Capacitancee Off State Input Capacitancee Off State Output Capacitancee Transition Time Break-Before-Make Interval SALVO, WR Turn On Time SALVO, WR Turn Off Time Charge Injection Matrix Disabled Crosstalk Adjacent Input Crosstalk All Hostile Crosstalk Bandwidth Symbol VANALOG rDS(on) rDS(on) IS(off) ID(off) ID(on) VAIH VAIL IAI IAO IDIS Tempb Full Room Full Room Room Full Room Full Room Full Full Full Room Full Room Room Room Typc Mind -5 Maxd 8 90 120 9 Mind -5 Maxd 8 90 120 9 Unit V 45 3 - 20 - 200 - 20 - 200 - 20 - 2000 2 0.1 - 600 1500 1.5 30 120 8 10 500 -1 - 10 20 200 20 200 20 2000 - 20 - 200 - 20 - 200 - 20 - 200 2 20 200 20 200 20 200 nA VAI = 0 V or 2 V or 5 V VAO = 2.7 V, See Truth Table VAO = 0.4 V, See Truth Table 0.8 1 10 - 200 -1 - 10 500 0.8 1 10 - 200 V A mA 40 160 20 20 20 20 300 10 300 500 175 300 10 300 175 pC ns pF CS(on) CS(off) CD(off) tTRANS tOPEN tON tOFF Q XTALK(DIS) XTALK(AI) XTALK(AH) BW 1 In to 1 Out, See Figure 11 1 In to 4 Out, See Figure 11 See Figure 11 Room Room Room Room Room Full Room Full Room Full Room Room Room Room Room See Figure 5 RL = 1 k, CL = 35 pF 50 % Control to 90 % Output See Figure 3 See Figure 6 RIN = RL = 75 f = 5 MHz, See Figure 10 RIN = 10 , RL = 10 k f = 5 MHz, See Figure 9 RIN = 10 , RL = 10 k f = 5 MHz, See Figure 8 RL = 50 , See Figure 7 - 100 - 82 - 85 - 66 300 dB MHz www.vishay.com 4 Document Number: 70071 S-71241-Rev. H, 25-Jun-07 DG884 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Specified V+ = 15 V, V- = - 3 V VL = 5 V, RS = 2.0 V SALVO, CS, WR, I/O = 0.8 V A Suffix - 55 to 125 C D Suffix - 40 to 85 C Unit Parameter Power Supplies Positive Supply Current Negative Supply Current Digital GND Supply Current Logic Supply Current Functional Operating Supply Voltage Rangee Symbol Tempb Room Full Typc 1.5 - 1.5 - 275 200 Mind Maxd 3 6 Mind Maxd 3 6 Unit I+ IIDG IL V+ to VV- to GND V+ to GND tAW tWP tWA tCW tWC tSP tSW tWS tIO tAO tCO tCA tRS tIA See Figure 1 See Operating Voltage Range (Typical Characteristics) page 6 All Inputs at GND or 2 V RS = 2 V Room Full Full Full Full Full Full Full Full Full Full Full Full Full Room Room Room Room Room Full Room -3 -5 - 750 500 13 - 5.5 10 20 0 20 -3 -5 - 750 500 13 - 5.5 10 50 100 10 100 75 100 10 50 200 200 200 100 50 20 0 20 mA A V Minimum Input Timing Requirements Address Write Time Minimum WR Pulse Width Write Address Time Chip Select Write Time Write Chip Select Time Minimum SALVO Pulse Width SALVO Write Time Write SALVOTime Input Output Time Address Output Time Chip Select Output Time Chip Select Address Time Reset to SALVO I/O Address Input Time 20 50 - 10 50 25 50 - 10 20 150 150 150 60 50 50 200 200 200 50 100 10 100 75 100 10 ns Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 70071 S-71241-Rev. H, 25-Jun-07 www.vishay.com 5 DG884 Vishay Siliconix TYPICAL CHARACTERISTICS 25 C, unless otherwise noted 120 120 100 X TALK(DIS) (- dB) X TALK(AI) (- dB) 100 80 80 60 60 40 40 20 1 10 f - Frequency (MHz) 100 20 1 10 f - Frequency (MHz) 100 Adjacent Input Crosstalk Matrix Disabled Crosstalk 100 21 80 V+ - Positive Supply (V) X TALK(AH) (- dB) 19 17 60 15 Operating Voltage Area 13 40 20 11 0 1 10 f - Frequency (MHz) 100 9 0 -1 - 2 - 3 - 4 - 5 - 6 V- - Negative Supply (V) All Hostile Crosstalk Operating Voltage Area www.vishay.com 6 Document Number: 70071 S-71241-Rev. H, 25-Jun-07 DG884 Vishay Siliconix TIMING DIAGRAMS CS for Device A CS for Device B tCA Address B0 B1 Address A0 A3 WR tIA SALVO tCW I/O tWC Input Select Output 1 Select Output 2 Output N Presetting Device A Donit Care Presetting Device B Donit Care Select Input tAW Select Input Input tWP tWA tAW tWA tWS tSW tAW tWA tWS tSW tSP tCW tSP RS Reset Occuring at Any Time Results In All Current Event Latches Being Cleared tRS Figure 1. Input Timing Requirements CS for Device A CS for Device B Address B0 B1 Address A0 A3 WR SALVO Output Interrogating Device A tC O Select Current Event Latch 1 Latch N Interrogating Device B tC O Select Current Event Latch t AO Address Output tC A tAO tAO tCA Out N tAO Address Output 1 tIO I/O RS Reset Occuring at Any Time Results In All Current Event Latches Being Cleared tIA Figure 2. Output Timing Requirements PARAMETER DEFINITIONS Symbol TAW TWA TWP TCW TWC TSP TWS TSW TIA TRS TIO TAO TCO TCA Parameter Address to Write Write to Address WR Pulse Chip Select to WR WR to Chip Select SALVO Pulse WR to SALVO SALVO to WR I/O to Address In RS to SALVO I/O to Output Address to Output CS to Output CS to Address In Description Minimum time address must be valid before WR goes high Minimum time address must remain valid after WR pulse goes high Minimum time of WR pulse width to write address into Next Event latches Minimum time chip select must be valid before a WR pulse Minimum time chip select must remain valid after WR pulse Minimum time of SALVO pulse width Minimum time from WR pulse to SALVOto load new address Minimum time from SALVO pulse to WR to load current address Minimum time I/O must be valid before address applied Minimum time RS must be valid before SALVO pulse Minimum time I/O must be valid before address output valid Minimum time address BX must be valid until address AX output valid Minimum time CS must be valid until AX output is valid Minimum time CS must be valid before address applied if I/O is high Document Number: 70071 S-71241-Rev. H, 25-Jun-07 www.vishay.com 7 DG884 Vishay Siliconix TEST CIRCUITS -3V V 1V IN1 GND DGND 1 k 35 pF VL 5V V+ VO OUT1 A0, A1, A2 SALVO 3V 0V 3V 50 % 0V 1V VO 90 % 90 % 50 % 15 V DG884 IN2 - IN8 SALVO A0, A1, A2 B0 B1 I/O CS WR A3 RS tON tOFF 3V Figure 3. SALVO Turn On/Off Time -3V V 1V IN1 GND DGND 1 k 35 pF 0V VO 1V 90 % 90 % VL 5V V+ VO OUT1 A0, A1, A2 WR 15 V 3V 0V 3V 50 % 50 % DG884 IN2 - IN8 WR A0, A1, A2 B0 B1 I/O CS SALVO A3 RS tON tOFF 3V Figure 4. WR Turn On/Off Time -3V V IN1 GND VO DGND IN8 IN2 - IN7 WR A0, A1, A2 B0 B1 I/O CS SALVO 90 % 1 k tTRANS tBBM A3 RS VL 5V V+ OUT1 VO A0, A1, A2 15 V 3V 0V 50 % 1V DG884 3V Figure 5. Transition Time and Break-Before-Make Interval www.vishay.com 8 Document Number: 70071 S-71241-Rev. H, 25-Jun-07 DG884 Vishay Siliconix TEST CIRCUITS -3V V IN1 GND DGND A3 WR A0, A1, A2 B B I/O CS SALVO RS 0 1 VL 5V V+ OUT1 VO 15 V -3V V IN8 VL 5V V+ 15 V Signal Generator 50 OUT1 VO 50 GND DGND WR A0 A3 DG884 35 pF DG884 A3 B0 B1 I/O CS SALVO WR RS V O 5V Q = V0 CL 5V Figure 6. Charge Injection Figure 7. -3 dB Bandwidth Any one input to any one output - all remaining inputs connected to remaining outputs VO Outputs RL 10 k 10 k Any input or output pin to adjacent input or output pin RL 10 k Vn - 1 Vn RIN 10 Vn + 1 RIN 10 Inputs Signal Generator 75 V X TA LK(AH) = 20 log 10 V OUT V Signal Generator 75 RIN 10 X TALK(AI) = 20 log10 Vn - 1 Vn or 20 log10 Vn + 1 Vn Figure 8. All Hostile Crosstalk Figure 9. Adjacent Input Crosstalk All crosspoints open Outputs RL 75 VO OUT 1 OUT 2 OUT 3 Meter Inputs HP4192A Impedance Analyzer or Equivalent IN2 IN3 IN4 IN5 DGND OUT 4 IN 1 GND DG884 VL RS I/O 5V IN 8 IN6 Signal Generator 75 IN7 X TALK(DIS) = 20 log10 V OUT V -3V 15 V Figure 10. Matrix Disabled Crosstalk Figure 11. On-State and Off-State Capacitances Document Number: 70071 S-71241-Rev. H, 25-Jun-07 V- V V+ CS "0" = Off-State "1" = On-State www.vishay.com 9 DG884 Vishay Siliconix PIN DESCRIPTION Pin 1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 41, 43 39 26 21 38 5, 7, 9, 11, 13, 15, 17, 19 2, 40, 42, 44 29 30 31, 32, 33, 34 27, 28 35 36 37 22, 23, 24, 25 Symbol GND DGND V+ VVL IN1 to IN8 OUT1 to OUT4 I/O CS A0, A1, A2, A3 B 0, B 1 WR SALVO RS DIS1 to DIS4 Analog Signal Ground Digital Ground Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage - generally 5 V 8 Analog Input Channels 4 Analog Output Channels Determines whether data is being written into the Next Event latches or read from the Current Event latches Chip Select - a logic input IN Address - logic inputs or outputs as defined by I/O pin, select one of eight IN channels OUT Address - logic inputs, select one of four OUT channels Write command that latches A0, A1, A2, A3 into the Next Event latches Master write command, that in one action, transfers all the data from Next Event latches into Current Event latches Reset - a low will clear the Current Event latches Open drain disable outputs - these outputs pull low when the corresponding OUT channel is off Description DEVICE DESCRIPTION The DG884 is the world's first monolithic wideband crosspoint array that operates from dc to > 100 MHz. The DG884 offers the ability to route any one of eight input signals to any one of four OUT pins. Any input can be routed to one, two, three or four OUTs simultaneously with no risk of shorting inputs together (guaranteed by design). Each crosspoint is configured as a "T" switch in which DMOS FETs are used due to their excellent low resistance and low capacitance characteristics. Each OUT line has a series switch that minimizes capacitive loading when the OUT is off. Interfacing The DG884 was designed to allow complex matrices to be developed while maintaining a simple control interface. The status of the I/O pin determines whether the DG884 is being written to or read from (see Figures 1 and 2). In order to WRITE to an individual latch, CS and I/O need to be low, while RS, WR and SALVO must be high. The IN to OUT path is selected by using address A0 through A3 to define the IN line and address B0 and B1 to define the OUT line. That is, The IN defined by A0 through A3 is electrically connected to the OUT defined by B0, B1. This chosen path is loaded into the Next Event latches when WR goes low and returns high again. This operation is repeated up to three more times if other crosspoint connections need to be changed. Upon completing all crosspoint connections that are to be changed in a single device, other DG884s can be similarly preset by taking the CS pin low on the appropriate device. When all DG884s are preset, the Current Event latches are simultaneously changed by a single SALVO command applied to all devices. In this manner the crosspoint configuration of any number of devices can be simultaneously updated. DIS Outputs Four open drain disable OUTs are provided to control external line drivers or to provide visual or electrical signaling. For example, any or all of the DIS OUTs can directly interface with a CLC410 Video Amplifier to place it into a high impedance, low-power standby mode when the corresponding OUT is not being used. (See Figure 15). The DIS outputs are low and sink to V- when corresponding OUT is open or RS is low. Reset The reset function (RS) allows the resetting of all crosspoints to a known state (open). At power up, the reset facility may be used to guarantee that all switches are open. It should be noted that RS clears the Current Event latches, but the Next Event latches remain unchanged. This useful facility allows the user to return the matrix to its previous state (prior to reset) by simply applying the SALVO command. Alternatively, the user can reprogram the Next Event latches, and then apply the SALVO command to reconfigure the matrix to a new state. www.vishay.com 10 Document Number: 70071 S-71241-Rev. H, 25-Jun-07 DG884 Vishay Siliconix DEVICE DESCRIPTION Readback The I/O facility enables the user to write data to the Next Event latches or to read the contents of the Current Event latches. This feature permits the central controller to periodically monitor the state of the matrix. If a power loss to the controller occurs, the readback feature helps the matrix to recover rapidly. It also offers a means to perform PC board diagnostics both in production and in system operation. 8 Analog Inputs EN CMOS Output Buffers Mux 1 8 4 / Data Buffers EN 4 8 Current Event / Mux 2 OUT1 I/O OUT2 RS A0 A1 A2 A3 B0 B1 CS WR Mux 3 Decoder SALVO DIS3 Open Drain Output Next Event Latch 3 Latch 3 Q0 Q3 4 / 7 / Decoders/ Drivers 9 / 8 T-Switches 1 Series Switch 8 OUT3 OUT4 Mux 4 One of Four Blocks of Logic/Latches Shown Figure 12. Control Circuitry APPLICATIONS Two-Si584 Quad Unity-Gain Buffers IN1 75 IN2 x1 x1 WR SALVO CLC410 75 x2 DIS1 x2 DIS2 OUT2 OUT1 DG884 DIS3 x2 OUT3 x2 DIS4 IN8 x1 RS OUT4 Note: DIS outputs are used to power down the Si582 amplifiers. RESET B0 B1 A0 A1 A2 A3 Figure 13. Fully Buffered 8 x 4 Crosspoint Document Number: 70071 S-71241-Rev. H, 25-Jun-07 www.vishay.com 11 DG884 Vishay Siliconix APPLICATIONS +5V + 15 V 51 51 6 C2 + C1 VL + C1 V+ C2 V th - Logic Threshold (V) C1 = 1 F Tantalum C2 = 100 nF Ceramic 5 4 DG884 3 V C1 + 51 3V C2 2 1 0 0 2 4 6 8 10 12 14 16 18 VL - Logic Supply (V) Figure 14. DG884 Power Supply Decoupling Figure 15. Switching Threshold Voltage vs. VL Power Supplies and Decoupling A useful feature of the DG884 is its power supply flexibility. It can be operated from dual supplies, or a single positive supply (V- connected to 0 V) if required. Allowable operating voltage ranges are shown in Operating Voltage Range (Typical Characteristics) graph, page 6. Note that the analog signal must not go below V- by more than 0.3 V (see absolute maximum ratings). However, the addition of a V- pin has a number of advantages: 1) It allows flexibility in analog signal handling, i.e. with V- = - 5 V and V+ = 15 V, up to 5 V ac signals can be accepted. The value of on-capacitance [CS(on)] may be reduced by increasing the value of V-. It is useful to note that optimum video differential phase and gain occur when V- is - 3 V. Note that V+ has no effect on CS(on). V- eliminates the need to bias an ac analog signal using potential dividers and large decoupling capacitors. Rules: 1) 2) 3) Decoupling capacitors should be incorporated on all power supply pins (V+, V-, VL). They should be mounted as close as possible to the device pins. Capacitors should have good high frequency characteristics - tantalum bead and/or monolithic ceramic disc types are suitable. Recommended decoupling capacitors are 1 to 10 F tantalum bead, in parallel with 100 nF monolithic ceramic. 4) Additional high frequency protection may be provided by 51 carbon film resistors connected in series with the power supply pins (see Figure 14). 2) 3) The VL pin permits interface to various logic types. The device is primarily designed to be TTL or CMOS logic compatible with + 5 V applied to VL. The actual logic threshold can be raised simply by increasing VL. It is established RF design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. The dynamic performance of the DG884 is adversely affected by poor decoupling of power supply pins. Also, since the substrate of the device is connected to the negative supply, proper decoupling of this pin is essential. www.vishay.com 12 Document Number: 70071 S-71241-Rev. H, 25-Jun-07 DG884 Vishay Siliconix APPLICATIONS A typical switching threshold versus VL is shown in Figure 15. These devices feature an address readback facility whereby the last address written to the device may be read by the system. This allows improved status monitoring and hand shaking without additional external components. When the I/O assigns the address output condition, the AX address pins can sink or source current for logic low and high, respectively. Note that VL is the logic high output condition. This point must be respected if VL is varied for input logic threshold shifting. Note: Even though these devices are designed to be latchup resistant, VL must not exceed V+ by more than 0.3 V in operation or during power supply on/off sequencing. Layout The PLCC package pinout is optimized so that large crosspoint arrays can be easily implemented with a minimum number of PCB layers (see Figure 16). Crosstalk is minimized and off-isolation is optimized by having ground pins located adjacent to each input and output signal pins. Optimum off-isolation and low crosstalk performance can only be achieved by the proper use of RF layout techniques: avoid sockets, use ground planes, avoid ground loops, bypass the power supplies with high frequency type capacitors (low ESR, low ESL), use striplines to maintain transmission line impedance matching. Address Bus Video Out Bus Video Out Bus Video In Bus Address Bus Video In Bus Video In Bus Video In Bus Video Out Bus Video Out Bus Figure 16. 16 X 8 Expandable Crosspoint Matrix Using DG884 Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70071. Document Number: 70071 S-71241-Rev. H, 25-Jun-07 www.vishay.com 13 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1 |
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